Due to advances in semiconductor manufacture, singulated semiconductor components, such as packages and dice, are becoming smaller, thinner, and lighter. For example, one type of semiconductor package is referred to as a "chip scale package" because it has a "footprint" (i.e., peripheral outline), and a thickness, that are about the same size as the die contained within the package. As singulated semiconductor components become smaller and lighter, it becomes more difficult to perform test procedures, such as burn-in. Testing of wafer sized components, such as wafers containing dice or chip scale packages, is also more difficult, as the wafers becoming thinner and more densely populated with individual components.
For performing test procedures on semiconductor components, test systems have been developed. The test systems include test circuitry for applying test signals to the integrated circuits contained on the components, and for analyzing the resultant signals. The test systems also include test carriers, or test boards, for retaining the components in electrical communication with the test circuitry. One type of test carrier comprises a temporary package which houses one, or more components, for mounting to a burn-in board. Alternately, test boards can be configured to directly retain multiple components in electrical communication with the test circuitry.
Representative test carriers are described in U.S. Pat. Nos. 5,519,332, 5,541,525, and 5,844,418 to Wood et al., U.S. Pat. No. 5,815,000 to Farnworth et al., and U.S. Pat. No. 5,783,461 to Hembree. A representative test board is described in U.S. Pat. No. 5,578,934 to Wood et al.
The test carriers and test boards include an interconnect for making temporary electrical connections with terminal contacts on the components. The terminal contacts on bare dice typically comprise planar aluminum bond pads, or alternately solder bumps on bond pads. The terminal contacts on chip scale packages typically comprise solder balls, arranged in a dense grid array, such as a ball grid array.
With either bumped or planar terminal contacts, the interconnects can include interconnect contacts, such as metallized recesses, or penetrating projections, that electrically engage the terminal contacts. For example, U.S. Pat. No. 5,592,736 to Akram et al. describes an interconnect with recessed contacts for electrically engaging bumped terminal contacts on unpackaged semiconductor dice. U.S. Pat. No. 5,686,317 to Akram et al. discloses an interconnect with penetrating projection contacts for electrically engaging planar terminal contacts on unpackaged semiconductor dice.
Prior to applying test signals, the components must be aligned with the interconnects, such that the interconnect contacts electrically engage the terminal contacts on the components. One method for aligning the components to the interconnects is with optical alignment techniques. With optical alignment, a viewing device can be configured to simultaneously view the interconnect contacts, and the terminal contacts. The viewing device provides feedback for manipulating vacuum tools for holding and placing the components on the interconnects. For example, an optical alignment system is described in U.S. Pat. Nos. 5,796,264 and 5,634,267 to Farnworth et al.
Although optical alignment techniques are suitable for volume semiconductor manufacture, the optical alignment systems are relatively complex, and are expensive to construct and maintain. For some applications, it may be preferable to employ mechanical alignment techniques. With mechanical alignment, an alignment member of the test system engages and aligns the components to the interconnects.
One type of alignment member includes an alignment opening, configured to engage the peripheral edges of a component. The component can be placed through the alignment opening and guided onto the interconnect. A representative mechanical alignment member is disclosed in U.S. Pat. No. 5,559,444 to Farnworth et al.
As semiconductor components become smaller, and the terminal contacts become more closely spaced, fabricating the alignment members with the required features and dimensional tolerances becomes more difficult. One problem is that the alignment members must be precisely aligned with the interconnects during fabrication of the test system. Misalignment of the alignment member with respect to the interconnect contacts during fabrication of the test system, can adversely affect the temporary electrical connections with the components during test procedures.
The present invention is directed to semiconductor test systems with improved alignment members for aligning the components. This invention also relates to fabrication process for the test systems and alignment members.